| PDC(4) | hp700 | PDC(4) |
The PDC version displayed at system boot is relevant to the particular system model and is not necessarily comparable to PDC versions on other systems.
| addr | contents |
| 0x00 | I-cache size in bytes |
| 0x04 | I-cache configuration |
| 0x08 | I-cache base for flushing |
| 0x0c | I-cache stride for flushing |
| 0x10 | I-cache count for flushing |
| 0x14 | I-cache loop size for flushing |
| 0x18 | D-cache size in bytes |
| 0x1c | D-cache configuration |
| 0x20 | D-cache base for flushing |
| 0x24 | D-cache stride for flushing |
| 0x28 | D-cache count for flushing |
| 0x2c | D-cache loop size for flushing |
| 0x30 | ITLB size |
| 0x34 | ITLB configuration |
| 0x38 | ITLB space base for flushing |
| 0x3c | ITLB space stride for flushing |
| 0x40 | ITLB space count for flushing |
| 0x44 | ITLB address base for flushing |
| 0x48 | ITLB address stride for flushing |
| 0x4c | ITLB address count for flushing |
| 0x50 | ITLB loop size for flushing |
| 0x54 | DTLB size |
| 0x58 | DTLB configuration |
| 0x5c | DTLB space base for flushing |
| 0x60 | DTLB space stride for flushing |
| 0x64 | DTLB space count for flushing |
| 0x68 | DTLB address base for flushing |
| 0x6c | DTLB address stride for flushing |
| 0x70 | DTLB address count for flushing |
| 0x74 | DTLB loop size for flushing |
The cache configuration word is formatted as follows:
| bit | len | contents |
| 0 | 12 | reserved |
| 13 | 3 | set 1 if coherent operation supported |
| 16 | 2 | flush mode: 0 -- fdc & fic; 1 -- fdc; 2 -- fic; 3 -- either |
| 18 | 1 | write-thru D-cache if set |
| 19 | 2 | reserved |
| 21 | 3 | cache line size |
| 24 | 4 | associativity |
| 28 | 4 | virtual address alias boundary |
The format of the NVM is as follows:
| offset | size | contents |
| 0x00 | 0x24 | HV dependent |
| 0x24 | 0x20 | bootpath |
| 0x44 | 0x04 | ISL revision |
| 0x48 | 0x04 | timestamp |
| 0x4c | 0x30 | LIF utility entries |
| 0x7c | 0x04 | entry point |
| 0x80 | 0x80 | OS panic information |
The format of the stable storage is as follows:
| offset | size | contents |
| 0x0000 | 0x20 | primary bootpath |
| 0x0020 | 0x20 | reserved |
| 0x0040 | 0x02 | OS ID |
| 0x0042 | 0x16 | OS dependent |
| 0x0058 | 0x02 | diagnostic |
| 0x005a | 0x03 | reserved |
| 0x005d | 0x02 | OS dependent |
| 0x005f | 0x01 | fast size |
| 0x0060 | 0x20 | console path |
| 0x0080 | 0x20 | alternative boot path |
| 0x00a0 | 0x20 | keyboard path |
| 0x00c0 | 0x20 | reserved |
| 0x00e0 | size | OS dependent |
The “OS ID” field may have the following values:
| value | OS |
| 0x000 | No OS-dependent info |
| 0x001 | HP-UX |
| 0x002 | MPE-iX |
| 0x003 | OSF |
| 0x004 | HP-RT |
| 0x005 | Novell Netware |
The “fast size” field is the amount of memory to be tested upon system boot and is a power of two multiplier for 256KB. Values of 0xe and 0xf are reserved.
Resetting the page table address and/or size without disabling the hardware TLB miss handler is allowed. Any changes made are immediate upon Code or Data virtual address translation bits are set in PSW.
Hewlett-Packard, PA-RISC 1.1 Firmware Architecture Reference Specification, March 8, 1999.
Hewlett-Packard, PA-RISC 2.0 Firmware Architecture Reference Specification, March 7, 1999.
| June 1, 2007 | NetBSD 5.99 |